1. Field of the Invention
The present invention relates to flash memory technology, and more particularly to flash memory suitable for low voltage program and erase in a NAND configuration.
2. Description of Related Art
Flash memory is a class of non-volatile integrated circuit memory technology. Traditional flash memory employs floating gate memory cells. As the density increases in memory devices, and the floating gate memory cells get closer and closer together, interference between the charge stored in adjacent floating gates becomes a problem. This is limiting the ability to increase the density of flash memory based on floating gate memory cells. Another type of memory cell used for flash memory can be referred to as a charge trapping memory cell, which uses a dielectric charge trapping layer in place of the floating gate. Charge trapping memory cells use dielectric charge trapping material that does not cause cell-to-cell interference like that encountered with floating gate technology, and is expected to be applied for higher density flash memory.
The typical flash memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a charge storage structure including a tunnel dielectric layer, the charge storage layer (floating gate or dielectric), and a blocking dielectric layer. According to the early conventional charge trapping memory designs referred to as SONOS devices, the source, drain and channel are formed in a silicon substrate (S), the tunnel dielectric layer is formed of silicon oxide (O), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed of silicon oxide (O), and the gate comprises polysilicon (S).
Flash memory devices generally are implemented using NAND or NOR architectures, although others are known, including AND architectures. The NAND architecture is popular for its high density and high speed when applied to data storage applications. The NOR architecture is better suited to other applications, such as code storage, where random byte access is important. In a NAND architecture, the programming processes typically rely on Fowler-Nordheim (FN) tunneling that require high voltages, such as on the order of 20 volts, and require high voltage transistors to handle them. The addition of high voltage transistors on integrated circuits, in combination with transistors used for logic and other data flow, introduces complexity in the manufacturing processes. This increased complexity in turn increases the costs of the devices.
Accordingly, it is desirable to provide a new memory technology suitable for low voltage programming operations, and which is configurable in a NAND architecture.